CHIPS for America R&D Facilities

Natcast and the Department of Commerce have launched a site selection process to identify three facilities:

• An NSTC Administrative and Design Facility
• An NSTC EUV Center
• NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility 

These R&D facilities demonstrate the CHIPS for America vision for engaging the full semiconductor ecosystem, from lab to fab. These vital new investments will drive the technologies of the future by providing a home for conducting world class R&D, fostering innovation, and reducing the time between early-stage research and commercialization. R&D initiatives may include, among others, new materials process architectures, device structures, novel design approaches, chiplets, heterogeneous integration, and advanced packaging. These efforts will support America’s global strength and leadership in design, materials, and process innovation while enabling a vibrant domestic industry.

The facilities model is informed by over a year of discussions with stakeholders building on the release of the NSTC Vision and Strategy Paper and the NAPMP Vision Paper, and robust analysis on the current and planned future state of the U.S. semiconductor manufacturing and R&D ecosystems.  A request for information published by Natcast in March 2024, collected feedback on the demand for prototyping facilities capabilities and also informed the facility model.

The Natcast and the Department of Commerce will select facilities deemed the most advantageous to the objectives of CHIPS for America, including based on an assessment of all the factors considered in each selection process. 

NSTC Administrative and Design Facility

The NSTC Administrative and Design Facility will be a multi-functional facility, serving as the location for key operations of the NSTC, including convening, design research, workforce efforts, and administrative offices.

This facility will:

• Host Natcast administrative functions and convening NSTC consortium members
• Conduct NSTC programmatic activity like the Workforce Center of Excellence and the NSTC Design Enablement Gateway
• Support advanced semiconductor research in chip design, electronic design automation, chip and system architecture, and hardware security

NSTC EUV Center

Given the high costs of developing and maintaining EUV tools, and the goal to provide access to these capabilities as soon as possible, Natcast expects to initially obtain access to EUV lithography for the NSTC through an agreement with an existing facility that meets the NSTC program requirements.

This facility will:

• Provide NSTC members with access to EUV technology to facilitate a wider range of research and a path to commercialization, including technologies with the most challenging feature sizes.
• Provide appropriate space for Natcast researchers and staff as well as member assignees to conduct research and collaborate in the facility.

NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility

The CHIPS R&D facilities model envisions co-located research and development for prototyping and advanced packaging capabilities to further both the NSTC and NAPMP programs. The Department and Natcast believe a dedicated facility will allow the NSTC and NAPMP to fully optimize the design of the facility to meet its mission. 

This facility will:

• Provide NSTC members with 300mm research and prototyping front-end manufacturing and packaging capabilities allowing for access to state-of-the-art and development of next-generation technologies
• Provide the domestic semiconductor ecosystem with unique value to conduct coordinated and collaborative front-end semiconductor and advanced packaging R&D

Note: this PDF of the Ecosystem Questionnaire is for reference only. All questionnaires must be submitted using the Formsite link emailed to EDOs. If you’re with the EDO of a state or territory and have questions on how to complete the questionnaire, email us at [email protected].

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